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d a t a sh eet product speci?cation supersedes data of 1999 mar 19 file under integrated circuits, ic19 1999 may 27 integrated circuits OQ2541hp; OQ2541u sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge
1999 may 27 2 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u features data and clock recovery up to 2.5 gbits/s multirate configurable (155, 622, 1250 or 2500 mbits/s) differential data input with 2.5 mv (p-p) typical sensitivity differential current-mode logic (cml) data and clock outputs with 50 w driving capability adjustable cml output level loop mode for system testing bit error rate related loss of signal detection few external components needed single supply voltage power dissipation 350 mw (typical value) lqfp48 plastic package. applications data and clock recovery in stm1/oc3, stm4/oc12 and stm16/oc48 transmission systems data and clock recovery in gigabit ethernet (ge) transmission systems. description the OQ2541 is a data and clock recovery ic intended for use in synchronous digital hierarchy (sdh) and synchronous optical network (sonet) systems. the circuit recovers data and extracts the clock signal from an incoming bitstream up to 2.5 gbits/s. it can be configured for use in stm1/oc3, stm4/oc12, stm16/oc48 and gigabit ethernet systems. ordering information type number package name description version OQ2541hp lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 OQ2541u - bare die; 2360 2360 380 m m -
1999 may 27 3 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u block diagram fig.1 block diagram. handbook, full pagewidth mbh972 frequency window detector (1000 ppm) + alexander phase detector frequency divider 1 1/2/4/16 frequency divider 2 64/128 data and clock output vcro 2.5 ghz proportional path integrating path power control 1 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47 13, 18, 19, 36, 40 9 33 28 30 15 16 21 22 enable 48 42 45 46 7 37 39 12 24 25 OQ2541 din 34 dinq dout622 dout155 27 dout1250 v ee1 31 v ee2 dout doutq cout coutq dloop dloopq cloop cloopq 43 los pc aref gnd 3 4 6 dref19 lock capupq capdoq dref39 cref crefq i.c. enl 130 pf 130 pf dt 17 5
1999 may 27 4 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u pinning symbol pin description enl 1 loop mode enable input (active low) gnd 2 ground; note 1 cloop 3 clock output in loop mode (differential) cloopq 4 inverted clock output in loop mode (differential) gnd 5 ground; note 1 dloop 6 data output in loop mode (differential) dloopq 7 inverted data output in loop mode (differential) gnd 8 ground; note 1 dref19 9 reference frequency select input 1 (see table 2) gnd 10 ground; note 1 gnd 11 ground; note 1 lock 12 phase lock detection output i.c. 13 internally connected; note 2 gnd 14 ground; note 1 capupq 15 external loop ?lter capacitor connection capdoq 16 external loop ?lter capacitor return connection gnd 17 ground; note 1 i.c. 18 internally connected; note 2 i.c. 19 internally connected; note 2 gnd 20 ground; note 1 cref 21 reference clock input (differential) crefq 22 inverting reference clock input (differential) gnd 23 ground; note 1 dref39 24 reference frequency select input 2 (see table 2) v ee1 25 negative supply voltage ( - 3.3 v); note 3 gnd 26 ground; note 1 dout1250 27 stm mode select input 1 (see table 3) dout622 28 stm mode select input 2 (see table 3) gnd 29 ground; note 1 dout155 30 stm mode select input 3 (see table 3) v ee2 31 negative supply voltage ( - 3.3 v); note 3 gnd 32 ground; note 1 din 33 data input (differential) dinq 34 inverting data input (differential) gnd 35 ground; note 1 i.c. 36 internally connected; note 2 pc 37 control output for negative power supply gnd 38 ground; note 1 los 39 loss of signal detection output i.c. 40 internally connected; note 2
1999 may 27 5 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u notes 1. all gnd pins or pads must be bonded; do not leave one single gnd pin or pad unconnected . 2. all pins or pads denoted i.c. should not be connected. connections to these pins or pads degrade device performance. 3. all v ee pins or pads must be bonded; do not leave one single v ee pin or pad unconnected . gnd 41 ground; note 1 dout 42 data output in normal mode (differential) doutq 43 inverted data output in normal mode (differential) gnd 44 ground; note 1 cout 45 clock output in normal mode (differential) coutq 46 inverted clock output in normal mode (differential) gnd 47 ground; note 1 aref 48 reference voltage input for controlling voltage swing on data and clock outputs symbol pin description fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 OQ2541hp mbh971 i.c. gnd dinq din v ee2 dout155 gnd dout622 dout1250 gnd v ee1 gnd gnd coutq cout gnd doutq dout i.c. los gnd pc aref gnd enl gnd cloop cloopq gnd dloop gnd dref19 gnd lock dloopq gnd gnd capupq capdoq gnd i.c. i.c. gnd crefq gnd dref39 i.c. cref
1999 may 27 6 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u functional description the OQ2541 recovers data and clock signals from an incoming high speed bitstream. the input signal on pins din and dinq is buffered and amplified by the input circuitry (see fig.1). the signal is then fed to the alexander phase detector where the phase of the incoming data signal is compared with that of the internal clock. if the signals are out of phase, the phase detector generates correction pulses (up or down) that shift the phase of the voltage controlled ring oscillator (vcro) output in discrete amounts ( dj ) until the clock and data signals are in phase. the technique used is based on principles first proposed by j.d.h. alexander, hence the name of the phase detector. data sampling the eye pattern of the incoming data is sampled at three instants a, t and b (see fig.3). when clock and data signals are synchronized (locked): a is the centre of the data bit t is in the vicinity of the next transition b is in the centre of the bit following the transition. if the same level is recorded at both a and b, a transition has not occurred and no action is taken regardless of the level t. however, if levels a and b are different a transition has occurred and the phase detector uses level t to determine whether the clock was too early or too late with respect to the data transition. if levels a and t are the same, but different from level b, the clock was too early and needs to be slowed down a little. the alexander phase detector then generates a down pulse which stretches a single output pulse from the ring oscillator by approximately 0.25% which is 1 ps of the 400 ps bit period in the stm16/oc48 mode. this forces the vcro to run at a slightly lower frequency for one bit period. the phase of the clock signal is thus shifted fractionally with respect to the data signal. fig.3 data sampling. handbook, halfpage mgk143 data data clock atb if, on the other hand, levels b and t are the same but different from level a, the clock was too late and needs to be speeded up for synchronization. the phase detector generates an up pulse forcing the vcro to run at a slightly higher frequency (+0.25%) for one bit period. the phase of the clock signal is shifted with respect to the data signal (as above, but in the opposite direction). only the proportional path is active while these phase adjustments are being made. because the instantaneous frequency of the vcro can be changed only in one of two discrete steps ( 0.25%), this type of loop is also known as a bang/bang phase-locked loop (pll). if not only the phase but also the frequency of the vcro is incorrect, a long train of up or down pulses will be generated. this pulse train is integrated to generate a control voltage that is used to shift the centre frequency of the vcro. once the correct frequency has been established, only the phase will need to be adjusted for synchronization. the proportional path adjusts the phase of the clock signal, whereas the integrating path adjusts the centre frequency. frequency window detector the frequency window detector checks the vcro frequency which must be within a 1000 ppm (parts per million) window around the required frequency. it compares the output of frequency divider 2 with the reference frequency on pins cref and crefq (19.44 or 38.88 mhz; see table 2). if the vcro frequency is found to be outside this window, the frequency window detector disables the alexander phase detector and forces the vcro output to a frequency within the window. the phase detector then starts acquiring lock again. because of the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. any crystal based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. since sampling point a is always in the centre of the eye pattern when the data and clock signals are in phase (locked), the values recorded at this point are taken as the retrieved data. the data and clock signals are available at the cml output buffers, which are capable of driving a 50 w load. rf data and clock input circuit the schematic of the input circuit is shown in fig.4. rf data and clock output circuit the schematic of the output circuit is shown in fig.5.
1999 may 27 7 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.4 rf data and clock input circuit. mgl669 v ee dinq, crefq din, cref 50 w 50 w fig.5 rf data and clock output circuit. handbook, halfpage mgl670 v aref v ee doutq, coutq 100 w 100 w dout, cout power supply and power control loop the OQ2541 contains an on-board voltage regulator. an external power transistor is needed to deliver the supply to this circuit. the required external circuit is straightforward, and can be built using a few components. a suitable circuit with a power supply of - 4.5 v is illustrated in fig.6. a different configuration could be used, as long as the power supply rejection ratio is greater than 60 db for all frequencies. the inductor is a rf choke with an impedance greater than 50 w at frequencies higher than 2 mhz. any transistor with a b > 100 and enough current sink capability can be used. the OQ2541 can also be used with a power supply of - 5.0 or - 5.2 v. the only adaptation to be made to the power control circuit is to change the emitter resistor r1 (see table 1). table 1 value of resistor r1. power supply resistor r1 - 4.5 v 2.0 w - 5.0 v 6.8 w - 5.2 v 8.2 w output amplitude reference the voltage swing at the cml compatible output stages (pins dout, doutq, cout, coutq, dloop, dloopq, cloop and cloopq) can be controlled by adjusting the voltage on pin aref (see fig.7). an internal voltage divider of 500 w and 16 k w connected between ground and v ee initially fixes this level. in most applications the outputs will be dc-coupled to a load of 50 w . the output level regulation circuit will maintain a 200 mv (p-p) single-ended swing across this load. the voltage on pin aref is half the single-ended peak-to-peak value of the output signal ( - 100 mv). no adjustments are necessary with dc-coupling. if the outputs are ac-coupled, the voltage on pin aref is half the single-ended peak-to-peak value of the output signal multiplied by a factor where r l is the external load and r o is the output impedance of the OQ2541 (100 w ). r l r o + r l --------------------
1999 may 27 8 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.6 schematic diagram of OQ2541 power control loop. (1) l1 = rf choke type murata blm21 or equivalent. handbook, full pagewidth 2 w r1 2 w 1 k w 1 k w 1 m f l1 (1) - 4.5 v b > 100 100 nf 3.3 nf mgl732 band gap reference v ee pc gnd off chip on chip fig.7 functionality of pin aref. handbook, halfpage mgl667 500 w 16 k w r aref v ee aref off chip on chip v aref gnd if the outputs are ac-coupled, the formulae for calculating the required voltage on pin aref and the value of the resistor connected between pins aref and v ee as follows: (1) and: (2) where r1 = 500 w , r2 = 16 k w and v ee = - 3.3 v. to maintain a single-ended swing of 200 mv (p-p) across a 50 w ac-coupled load, the voltage on pin aref must be this can be achieved by connecting a 7.3 k w resistor between pins aref and v ee . v aref r l r o + r l -------------------- 0.5v swing C = r aref r1 v ee v aref ---------------- - 1 C ? ? ?? 1 r1 r2 ------- - v ee v aref ---------------- - 1 C ? ? ?? ? ? ?? C ---------------------------------------------------------------- = 100 mv C 50 + 100 ()w 50 w ---------------------------------- - 300 mv C =
1999 may 27 9 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u external capacitor for loop ?lter the loop filter is an integrator with a built-in capacitance of 2 130 pf. an external capacitance of 200 nf must be connected between pins capupq and capdoq to ensure loop stability while the frequency window detector is active. loop mode enable the loop mode is provided for system testing (see fig.8). the loop mode is enabled by applying a voltage lower than 0.8 v (ttl low-level) to pin enl. this selects the loop mode: the outputs on pins dloop, dloopq, cloop and cloopq are switched on. if a voltage higher than 2.0 v (ttl high-level) is applied to pin enl, then pins dout, doutq, cout and coutq are switched on while pins dloop, dloopq, cloop and cloopq are disabled to minimize power consumption. if pin enl is connected to v ee ( - 3.3 v), all outputs are enabled. lock detection pin lock should be interpreted as an indication for the presence of the reference clock on pin cref and for properly functioning of the acquisition aid (frequency window detector). fig.8 input circuit of pin enl. handbook, halfpage mgl668 decoder logic enl gnd v ee 36 k w off chip on chip pin lock is an open-collector ttl output and should be pulled up with a 10 k w resistor to a positive supply voltage. if the vco frequency is within a 1000 ppm window around the desired frequency, pin lock will remain at a high-level. if no reference clock is present, or the vco is outside the 1000 ppm window, pin lock will be at a low-level. the logic level on pin lock does not indicate locking of the pll to the incoming data; this is indicated by the signal on pin los. loss of signal detection the loss of signal (los) function is closely related to the functionality of the alexander phase detector; see fig.3 for the meaning of a, b and t in this section. in the functional description it is described that the phase detector does not take any action if the value at sample points a and b are the same, because there has not been any transition. however, if levels a and b are the same but different from level t, this still means there has not been any transition, but level t has got the wrong level somehow. this is probably due to noise or bad signal integrity, which will lead to a bit error. hence the occurrence of this particular situation is an indication for bit errors. if too many of these bit errors occur per time and the pll is gradually losing lock, the los alarm is asserted. the los alarm assert level is around a bit error rate (ber) for ber = 5 10 - 2 and the de-assert level is around ber = 1 10 - 3 . the los function will only work properly if the input signal is larger than the input offset of the OQ2541; otherwise, the signal will be masked by the input offset and interpreted as consecutive bits of the same sign, thus obstructing a proper los detection. in practice an optical front-end device with a noise level (rms value) larger than the specified offset of the OQ2541 will ensure a proper los indication. the los detection is ber related, but neither dependent on the data stream content, nor protocol. therefore, an sdh/sonet data stream is no prerequisite for a proper los function. since the los function of the OQ2541 is derived from digital signals, it is a good supplement to an analog, amplitude based, los indication. pin los is an open-collector ttl compatible output. a pull-up resistor should be connected to a positive supply voltage. pin los will be at a high-level (ttl) if the data signal is absent on pins din and dinq or if ber > 5 10 - 2 ; otherwise pin los will be at a low-level if ber < 1 10 - 3 .
1999 may 27 10 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u reference frequency select a reference clock signal of 19.44 or 38.88 mhz must be connected to pins cref and crefq. it should be noted that the reference frequency should be either 39.0625 mhz or 19.53125 mhz in a gigabit ethernet system. pins dref19 and dref39 are used to select the appropriate output frequency at frequency divider 2 (see table 2). to minimize the adverse influence of reference clock crosstalk, a differential signal with an amplitude from 75 to 150 mv (p-p) is advised. since the reference clock is only used as an acquisition aid for the pll of the frequency window detector, the quality of the reference clock (i.e. phase noise) is not important. there is no phase noise specification imposed on the reference clock generator and even frequency stability may be in the order of 100 ppm. in general, most inexpensive crystal based oscillators are suitable. when the OQ2541 is used in an application with a fixed reference clock frequency, it is best to connect the planes of pins dref19 and dref39 with a short trace or a via to the plane of pin gnd or pin v ee . if a selectable reference clock frequency is required in the application, the pins can be controlled through low ohmic switching fets, e.g. bsh103 or equivalent (low r dson ). table 2 reference frequency selection stm mode selection the vcro has a very large tuning range. however, the performance of the OQ2541 is optimized for sdh/sonet bit rates. frequenc y (mhz) division factor level on pin dref19 dref39 38.88 64 ground v ee 19.44 128 v ee v ee due to the nature of the pll, the very wide tuning range is a necessity for proper lock behaviour over the guaranteed temperature range, aging and batch to batch spread. though it might seem that the OQ2541 is capable of recovering other bit rates than sdh/sonet and gigabit ethernet rates (stm1/oc3, stm4/oc12, stm16/oc48 and 1250 mbits/s), the behaviour can not be guaranteed. the required sdh/sonet bit rate is selected by connecting pins dout155, dout622 and dout1250 to ground or to the supply voltage v ee (see table 3): for stm16/oc48 (2488.32 mbits/s) operation: all three pins must be connected to ground for gigabit ethernet (1250 mbits/s) operation: pin dout1250 must be connected to v ee for stm4/oc12 (622.08 mbits/s) operation: pins dout1250 and dout622 must be connected to v ee (the dividers are daisy chained) for stm1/oc3 (155,52 mbits/s) operation: all three pins must be connected to v ee . the connections to v ee and ground carry a current of a few milliamperes and should have low resistance and inductance, so short printed-circuit board tracks are recommended. in some cases a decoupling capacitor near the selection pins can be necessary to provide a clean return path for rf signals. when the OQ2541 is used in an application with a fixed data rate, it is best to connect the planes of pins dout155, dout622 and dout1250 with a short trace or a via to the plane of pin gnd or pin v ee . if a selectable reference clock frequency is required in the application, the pins can be controlled through low-ohmic switching fets, e.g. bsh103 or equivalent (low r dson ). table 3 stm mode select mode bit rate (mbits/s) division factor level on pin dout155 dout622 dout1250 stm1/oc3 155.52 16 v ee v ee v ee stm4/oc12 622.08 4 ground v ee v ee gigabit ethernet 1250.00 2 ground ground v ee stm16/oc48 2488.32 1 ground ground ground
1999 may 27 11 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u application with positive supply voltage due to the versatile design of the OQ2541 the device can also operate in a positive supply voltage application, although some pins have a different mode of operation. this section deals with these differences and supports the user with achieving a successful application of the OQ2541 in a +5 v environment. a pplication diagram a sample application diagram can be found in fig.29. it should be noted that all pins gnd are now connected to v cc and all pins v ee are connected to the regulated voltage from the power controller. o utput selection in a positive supply voltage application, the loop mode is the default rf output. due to the decoding logic on pin enl, it is only possible to select the loop mode outputs or enable all the outputs. if pin enl is connected to v cc (+5 v), only the loop mode outputs are active (see table 4). when pin enl is connected to v ee (the voltage is approximately 3.3 v below v cc ) all outputs become active. in the positive supply voltage application the normal mode outputs can not be selected, unless the voltage on pin enl is 2 v above the positive supply voltage (v cc ). caution do not to connect pin enl to ground, because this will destroy the ic. l oss of signal and lock detection in the negative supply application, pins los and lock are open-collector outputs that require pull-up resistors to a positive supply voltage. in the positive supply application, the pull-up voltage would need to be higher then the positive supply voltage and the signals on pins los and lock would not be ttl compatible any more. however, the internal circuit on pins los and lock can be used in a current mirror configuration (see fig.9). this requires only an external pnp transistor (e.g. bc857 or equivalent) to mirror the current. a 10 k w pull-down resistor from the collector of the external transistor to ground yields a ttl compatible signal again, albeit inverted. table 5 shows the meaning of the los and lock flag, when used in the positive supply application. fig.9 signal out for los and lock indication in a positive supply voltage application. handbook, halfpage mgl671 gnd bc857 + 5 v signal out los, lock 10 k w off chip on chip table 4 output selection in a positive supply voltage application table 5 los and lock indication in a positive supply voltage application mode level on pin enl output dloop, dloopq, cloop and cloopq dout, doutq, cout and coutq loop v cc (+5 v) active - loop and normal v ee (v cc - 3.3 v) active active normal v cc +2v - active signal description level ttl los active loss of signal: ber > 5 10 - 2 0 v (ground) low los inactive no loss of signal: ber < 1 10 - 3 +5 v (v cc ) high lock active reference clock present and vcro inside 1000 ppm window 0 v (ground) low lock inactive no reference clock present or vcro outside 1000 ppm window +5 v (v cc ) high
1999 may 27 12 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u d ivider settings the reference frequency dividers and the stm mode selectors still operate the same in a positive supply voltage application. the only difference is that pins formerly connected to ground should now be connected to v cc (+5 v). pins connected to v ee should still be connected to v ee because connecting these pins to ground (0 v) will damage the ic. rf input and outputs all rf inputs, outputs and internal signals of the OQ2541 are referenced to pins gnd. in the positive supply voltage application, this means that all rf signals are referenced to v cc . therefore a clean v cc rail is of ultimate importance for proper rf performance. the best performance is obtained when the transmission line reference plane is also decoupled to v cc . careful design of v cc and good decoupling schemes should be taken into account. while designing the printed-circuit board, bear in mind that the v cc has become what was formerly ground. while laying out the application, the return path is the most important issue to be considered. it is always advised to examine carefully the current carrying loops in the design. care should be taken that for all frequencies (both of interest and not of interest) low ohmic and low inductance return paths are available. these return paths should preferably have an enclosed area as small as possible, both horizontally and vertically (by means of through-holes or vias). the position of a decoupling capacitor is very important. a decoupling capacitor on an unfavourable position could do more damage than completely omitting the capacitor, while on the right location it can mean the difference between mediocre results and the ultimate achievement.
1999 may 27 13 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u limiting values in accordance with the absolute maximum rating system (iec 134). handling instructions precautions should be taken to avoid damage through electrostatic discharge. this is particularly important during assembly and handling of the bare die. additional safety can be obtained by bonding the v ee and gnd pads first, the remaining pads may then be bonded to their external connections in any order. thermal characteristics note 1. thermal resistance from junction to ambient is determined with the ic soldered on a standard single sided 57 57 1.6 mm fr4 epoxy pcb with 35 m m thick copper traces. the measurements are performed in still air. symbol parameter min. max. unit v ee negative supply voltage - 6 +0.5 v v n dc voltage on pins cloop, cloopq, dloop, dloopq, cref, crefq, din, dinq, dout, doutq, cout and coutq - 1 +0.5 v enl, lock and los, v ee - 0.5 +5.5 v dref19, dref39, dout1250, dout622, dout155, pc and aref v ee - 0.5 +0.5 v capupq and capdoq v ee + 0.5 - 0.5 v i n input current on pins enl - 1ma cref, crefq, din and dinq - 20 +10 ma p tot total power dissipation - 700 mw t amb ambient temperature - 40 +85 c t j junction temperature - 40 +110 c t stg storage temperature - 65 +150 c symbol parameter conditions value unit r th(j-s) thermal resistance from junction to solder point 46 k/w r th(j-a) thermal resistance from junction to ambient in free air; note 1 67 k/w
1999 may 27 14 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u characteristics v ee = - 3.3 v; t amb = - 40 to +85 c; typical values measured at t amb =25 c; all voltages are measured with respect to gnd. symbol parameter conditions min. typ. max. unit supply v ee negative supply voltage see fig.12; note 1 - 3.50 - 3.30 - 3.10 v i ee negative supply current open outputs; see fig.13 - 105 155 ma p tot total power dissipation - 350 550 mw data and clock inputs: pins din, dinq, cref and crefq v i(p-p) input voltage (peak-to-peak value) 50 w measurement system; see fig.10; notes 2 and 3 7 200 450 mv v i(sens)(p-p) input sensitivity (peak-to-peak value) 50 w measurement system; notes 2 and 4 - 2.5 7 mv v io dc input offset voltage 50 w measurement system - 3 0 +3 mv v i input voltage 50 w measurement system - 600 - 200 +250 mv z i input impedance single-ended; see fig.4; note 5 - 50 -w data and clock outputs: pins dout, doutq, dloop, dloopq, cout, coutq, cloop and cloopq v o(p-p) output voltage swing (peak-to-peak value) 50 w measurement system; single-ended; see fig.10 default adjustment; note 6 170 200 210 mv special adjustment; note 7 50 - 400 mv v o output voltage - 600 - 0mv z o output impedance single-ended - 100 -w t r(c) clock output rise time differential; 20% to 80% - 54 - ps t f(c) clock output fall time differential; 20% to 80% - 54 - ps t r(d) data output rise time differential; 20% to 80% - 116 - ps t f(d) data output fall time differential; 20% to 80% - 116 - ps t d(d-c) data-to-clock delay see fig.11; note 8 250 280 310 ps output amplitude adjustment: pin aref v aref output amplitude reference voltage ?oating pin - 110 - 100 - 90 mv power control output: pin pc g m transconductance - 84 - 60 - 42 ma/v i o output current 1 - 3.5 ma loop mode enable input: pin enl v il low-level input voltage -- 0.8 v v ih high-level input voltage 2.0 -- v phase lock indicator: pin lock v ol low-level output voltage note 9 - 0.6 -- v v oh high-level output voltage note 9 -- 3.3 v
1999 may 27 15 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u loss of signal indicator: pin los v ol low-level output voltage note 9 - 0.6 -- v v oh high-level output voltage note 9 -- 3.3 v t as assert time note 10 - 0.1 -m s t das de-assert time note 10 - 10 -m s ber as assert bit error rate note 10 - 5 10 - 2 - ber ber das de-assert bit error rate note 10 - 1 10 - 3 - ber pll characteristics t acq acquisition time cref = 19.44 mhz - 100 200 m s cref = 38.88 mhz - 50 200 m s j tol(p-p) jitter tolerance (peak-to-peak value) stm1/oc3 mode; note 11 f = 6.5 khz 1.5 >10 - ui f = 65 khz 0.15 1.3 - ui f = 1 mhz 0.15 0.8 - ui stm4/oc12 mode; note 11 f = 25 khz 1.5 >10 - ui f = 100 khz 0.7 3 - ui f = 250 khz 0.15 1.3 - ui f = 1 mhz 0.15 0.50 - ui f = 5 mhz 0.15 0.35 - ui stm16/oc48 mode; note 11 f = 100 khz 1.5 >10 - ui f = 1 mhz 0.15 1.1 - ui f = 10 mhz 0.15 0.23 - ui j gen(p-p) jitter generation (peak-to-peak value) stm1/oc3 mode; note 12 f = 500 hz to 1.3 mhz - 0.039 0.50 ui f = 12 khz to 1.3 mhz - 0.032 0.10 ui f = 65 khz to 1.3 mhz - 0.032 0.10 ui stm4/oc12 mode; note 12 f = 1 khz to 5 mhz - 0.050 0.50 ui f = 12 khz to 5 mhz - 0.040 0.10 ui f = 250 khz to 5 mhz - 0.052 0.10 ui stm16/oc48 mode; note 12 f = 5 khz to 20 mhz - 0.079 0.50 ui f = 12 khz to 20 mhz - 0.063 0.10 ui f=1to20mhz - 0.053 0.10 ui symbol parameter conditions min. typ. max. unit
1999 may 27 16 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u notes 1. typical power supply voltage for the voltage regulator is - 4.5 v (see fig.6). 2. it is assumed that both cml inputs carry a complementary signal with the specified peak-to-peak value (true differential excitation). 3. the specified input voltage range is the guaranteed and tested range for proper operation; ber < 1 10 - 10 . 4. an input sensitivity of 7 mv (p-p) for ber < 1 10 - 10 is guaranteed. the typical input sensitivity for ber < 1 10 - 10 is 2.5 mv (p-p). 5. cml inputs are terminated internally using on-chip resistors of 50 w connected to ground. 6. output voltage range with default reference voltage on pin aref (floating). 7. output voltage range with adjustment of voltage on pin aref (see section output amplitude reference). 8. measured with 1010 data pattern, single-ended output signals and rising edges of the signals on pins cout to dout or pins cloop to dloop. it should be noted that small deviations of the specified value are possible if measured differentially. 9. external pull-up resistor of 10 k w connected to supply voltage of +3.3 v. 10. los assert or de-assert timing and ber level are for indication only. the values are neither production tested nor guaranteed. 11. measured in accordance with itu specification g.958. measured on demoboard om5801 for stm16/oc48 and demoboard om5802 for stm1/oc3 and stm4/oc12. see for more information application note an96051 and application note an97065 . 12. measured in accordance with itu specification g.813 and 1 db above the system input sensitivity power level. measured on demoboard om5801 for stm16/oc48 and on demoboard om5802 for stm1/oc3 and stm4/oc12. 13. tdr is bit rate independent. j gen(rms) jitter generation (rms value) stm1/oc3 mode; note 12 f = 500 hz to 1.3 mhz - 0.0060 - ui f = 12 khz to 1.3 mhz - 0.0046 - ui f = 65 khz to 1.3 mhz - 0.0041 - ui stm4/oc12 mode; note 12 f = 1 khz to 5 mhz - 0.0093 - ui f = 12 khz to 5 mhz - 0.0079 - ui f = 250 khz to 5 mhz - 0.0081 - ui stm16/oc48 mode; note 12 f = 5 khz to 20 mhz - 0.0143 - ui f = 12 khz to 20 mhz - 0.0139 - ui f=1to20mhz - 0.0079 - ui tdr transitionless data run note 13 - 2000 - bits symbol parameter conditions min. typ. max. unit
1999 may 27 17 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.10 logic level symbol definitions for cml. handbook, full pagewidth mgk144 v io v i(max) v iqh v ih v iql v il v i(min) v i(p-p) gnd cml input v oo v o(max) v oqh v oh v oql v ol v o(min) v o(p-p) gnd cml output fig.11 data-to-clock delay for cml outputs: cout to dout or cloop to dloop. handbook, full pagewidth mgl672 gnd t d(d-c) - 200 mv gnd cout or cloop dout or dloop - 200 mv
1999 may 27 18 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u typical performance characteristics fig.12 supply voltage as a function of the temperature. it should be noted that the voltage on pins v ee is regulated by the power controller. handbook, halfpage - 40 - 3.30 - 3.35 - 3.40 - 3.45 0 40 120 80 v ee (v) t ( c) mgl650 fig.13 supply current as a function of the temperature. handbook, halfpage - 40 0 40 120 160 120 40 0 80 80 t ( c) i ee (ma) mgl649 fig.14 clock output rise time as a function of the temperature. measured on single-ended output. handbook, halfpage - 40 0 40 120 80 60 76 80 t ( c) t r(c) (ps) 72 68 64 mgl653 fig.15 clock output fall time as a function of the temperature. measured on single-ended output. handbook, halfpage - 40 0 40 120 70 50 66 80 t ( c) t f(c) (ps) 62 58 54 mgl652
1999 may 27 19 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.16 data output rise time as a function of the temperature. measured on single-ended output. handbook, halfpage - 40 170 160 150 140 0 40 120 80 t r(d) (ps) t ( c) mgl655 fig.17 data output fall time as a function of the temperature. measured on single-ended output. handbook, halfpage - 40 0 40 120 110 100 80 70 90 80 t ( c) t f(d) (ps) mgl654 fig.18 data-to-clock delay time as a function of the temperature. see fig.11 for the definition of t d . handbook, halfpage - 40 0 40 120 300 200 280 80 t ( c) t d(d-c) (ps) 260 240 220 mgl651
1999 may 27 20 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.19 bit error rate as a function of the input signal in stm1/oc3 mode (155.52 mbits/s). a complementary input signal of the indicated value is applied to pins din and dinq. handbook, halfpage 10 - 11 10 - 10 10 - 9 10 - 8 10 - 7 10 - 6 10 - 5 10 - 4 10 - 3 10 - 2 10 - 1 1 1.5 0.5 1 0 ber v i(p-p) (mv) mgl658 fig.20 bit error rate as a function of the input signal in stm4/oc12 mode (622.08 mbits/s). a complementary input signal of the indicated value is applied to pins din and dinq. handbook, halfpage 10 - 11 10 - 10 10 - 9 10 - 8 10 - 7 10 - 6 10 - 5 10 - 4 10 - 3 10 - 2 10 - 1 1 1.5 0.5 1 0 ber v i(p-p) (mv) mgl657
1999 may 27 21 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.21 bit error rate as a function of the input signal in stm16/oc48 mode (2488.32 mbits/s). a complementary input signal of the indicated value is applied to pins din and dinq. handbook, halfpage 10 - 11 10 - 10 10 - 9 10 - 8 10 - 7 10 - 6 10 - 5 10 - 4 10 - 3 10 - 2 10 - 1 1 1.5 0.5 1 0 ber v i(p-p) (mv) mgl656
1999 may 27 22 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.22 jitter tolerance as a function of the jitter frequency in the stm1/oc3 mode (155.52 mbits/s). (1) device performance measured on om5802 demoboard. (2) itu specification template. handbook, full pagewidth mgl659 10 3 10 2 10 1 10 - 1 1 (1) 10 j tol(p-p) (ui) f (khz) 10 2 10 3 10 4 (2) fig.23 jitter tolerance as a function of the jitter frequency in the stm4/oc12 mode (622.08 mbits/s). (1) device performance measured on om5802 demoboard. (2) itu specification template. handbook, full pagewidth mgl660 10 3 10 2 10 1 10 - 1 1 (1) (2) 10 10 2 10 3 10 4 j tol(p-p) (ui) f (khz)
1999 may 27 23 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.24 jitter tolerance as a function of the jitter frequency in the stm16/oc48 mode (2488.32 mbits/s). (1) device performance measured on om5801 demoboard. (2) itu specification template. handbook, full pagewidth mgl661 10 3 10 2 10 1 10 - 1 11010 2 10 3 10 4 (1) (2) j tol(p-p) (ui) f (khz)
1999 may 27 24 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.25 data and clock output waveforms in the stm4/oc12 mode (622.08 mbits/s). measured single-ended. handbook, full pagewidth mgs228 200 mv/div fig.26 data and clock output waveforms in the stm16/oc48 mode (2488.32 mbits/s). measured single-ended. handbook, full pagewidth mgs229 200 mv/div
1999 may 27 25 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u application information fig.27 application diagram showing the OQ2541 configured for the stm16/oc48 mode (2488.32 mbits/s). (1) all pins gnd must be connected directly to the pcb ground plane (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). (2) l1 = rf choke type murata blm21. handbook, full pagewidth 2 w 2 w 1 k w 1 k w 1 m f l1 (2) - 4.5 v + 3.3 v b > 100 100 nf 3.3 nf mbh973 v ee2 pc gnd (1) 1 3 4 6 7 45 46 42 43 9 27 28 30 17 15 16 21 22 48 37 31 v ee1 25 24 OQ2541 normal output loop output output select dout1250 coutq cout doutq dout 12 lock aref cloop cloopq dloop dref19 39 mhz system clock dloopq capupq capdoq crefq dref39 cref enl dout155 dout622 10 k w + 3.3 v 39 los 10 k w 100 nf 100 nf 34 33 dinq din pre- amp 13, 18, 19, 36, 40 i.c. 5
1999 may 27 26 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.28 application diagram showing the OQ2541 configured for the stm4/oc12 mode (622.08 mbits/s). (1) all pins gnd must be connected directly to the pcb ground plane (pins 2,5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). (2) l1 = rf choke type murata blm21. handbook, full pagewidth 2 w 2 w 1 k w 1 k w 1 m f l1 (2) - 4.5 v + 3.3 v b > 100 100 nf 3.3 nf mgl662 v ee2 v ee1 pc gnd (1) 1 3 4 6 7 45 46 42 43 9 34 33 27 28 30 17 15 16 21 22 48 37 31 25 24 OQ2541 normal output loop output output select dinq din pre- amp dout1250 coutq cout doutq dout 12 lock aref cloop cloopq dloop dref19 39 mhz system clock dloopq capupq capdoq crefq dref39 cref enl dout155 dout622 10 k w + 3.3 v 39 los 10 k w 100 nf 100 nf 13, 18, 19, 36, 40 i.c. 5
1999 may 27 27 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u fig.29 application diagram showing the OQ2541 configured for the stm16/oc48 mode (2488.32 mbits/s) with a positive supply voltage application. (1) (1) all pins gnd must be connected directly to v cc on the pcb plane of +5 v (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). (2) l1 = rf choke type murata blm21. (3) the loop mode outputs are used as main outputs: pin enl = high-level selects loop mode outputs pin enl = low-level selects loop mode and normal mode outputs simultaneously. handbook, full pagewidth 2 w 2 w 1 k w 1 k w 1 m f l1 (2) b > 100 100 nf 3.3 nf mgl663 v ee2 v ee1 pc gnd (1) 1 3 4 6 7 45 46 42 43 9 34 33 27 28 30 17 15 16 21 22 48 37 31 25 24 OQ2541 normal output unused output loop output output select dinq din pre- amp dout1250 coutq cout doutq dout 12 lock lock aref v cc v cc v cc v cc v cc v cc cloop cloopq dloop dref19 39 mhz system clock dloopq capupq capdoq crefq dref39 cref enl dout155 dout622 39 los los 10 k w 100 nf 100 nf = main output (3) = v cc 10 k w 13, 18, 19, 36, 40 i.c. 5
1999 may 27 28 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u bonding pads fig.30 bonding pad locations of OQ2541u. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 12 enl gnd cloop cloopq gnd dloop dloopq gnd dref19 gnd gnd lock 36 35 34 33 32 31 30 29 28 27 26 25 i.c. dinq gnd din gnd v ee2 dout155 gnd dout622 dout1250 gnd v ee1 24 23 22 21 20 19 18 17 16 15 14 13 i.c. gnd capupq capdoq gnd i.c. i.c. gnd cref crefq gnd dref39 coutq cout gnd aref gnd doutq dout gnd i.c. los gnd pc 37 38 39 40 41 42 43 44 45 46 47 48 OQ2541u x y 0 0 mgl664 2.360 mm 2.360 mm
1999 may 27 29 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u table 6 bonding pad locations. symbol pad coordinates (1) xy enl 1 - 1017.5 +852.5 gnd 2 - 1017.5 +697.5 cloop 3 - 1017.5 +542.5 cloopq 4 - 1017.5 +387.5 gnd 5 - 1017.5 +232.5 dloop 6 - 1017.5 +77.5 dloopq 7 - 1017.5 - 77.5 gnd 8 - 1017.5 - 232.5 dref19 9 - 1017.5 - 387.5 gnd 10 - 1017.5 - 542.5 gnd 11 - 1017.5 - 697.5 lock 12 - 1017.5 - 852.5 i.c. 13 - 852.5 - 1017.5 gnd 14 - 697.5 - 1017.5 capupq 15 - 542.5 - 1017.5 capdoq 16 - 387.5 - 1017.5 gnd 17 - 232.5 - 1017.5 i.c. 18 - 77.5 - 1017.5 i.c. 19 +77.5 - 1017.5 gnd 20 +232.5 - 1017.5 cref 21 +387.5 - 1017.5 crefq 22 +542.5 - 1017.5 gnd 23 +697.5 - 1017.5 dref39 24 +852.5 - 1017.5 v ee1 25 +1017.5 - 852.5 gnd 26 +1017.5 - 697.5 dout1250 27 +1017.5 - 542.5 dout622 28 +1017.5 - 387.5 gnd 29 +1017.5 - 232.5 dout155 30 +1017.5 - 77.5 v ee2 31 +1017.5 +77.5 gnd 32 +1017.5 +232.5 din 33 +1017.5 +387.5 dinq 34 +1017.5 +542.5 gnd 35 +1017.5 +697.5 i.c. 36 +1017.5 +852.5 pc 37 +852.5 +1017.5 gnd 38 +697.5 +1017.5 note 1. all x and y coordinates represent the position of the centre of the pad in m m with respect to the centre of the die (see fig.30). los 39 +542.5 +1017.5 i.c. 40 +387.5 +1017.5 gnd 41 +232.5 +1017.5 dout 42 +77.5 +1017.5 doutq 43 - 77.5 +1017.5 gnd 44 - 232.5 +1017.5 cout 45 - 387.5 +1017.5 coutq 46 - 542.5 +1017.5 gnd 47 - 697.5 +1017.5 aref 48 - 852.5 +1017.5 symbol pad coordinates (1) xy
1999 may 27 30 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u table 7 physical characteristics of bare die thermal considerations to improve heat transfer away from the product, a large area fill is recommended as a die pad. the die should be mounted on this with a heat conductive glue. bonding all supply and ground pads is essential for the electrical performance, but also improves heat transfer to the die pad or other copper area fills. the more copper is leading away from the die, the better the heat transport. on its turn, this copper should be able to loose its heat to the environment through radiation, natural convection (non forced airflow over the printed-circuit board) or forced cooling. name description glass passivation 0.8 m m silicon nitride on top of 0.9 m m psg (phosphosilicate glass) bonding pad dimension minimum dimension of exposed metallization is 90 90 m m (pad size = 100 100 m m) metallization 1.8 m m alcu (1% cu) thickness 380 m m nominal size 2.360 2.360 mm (5.5696 mm 2 ) backing silicon; electrically connected to v ee potential through substrate contacts attache temperature <440 c; recommended die attache is glue attache time <15 s
1999 may 27 31 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 94-12-19 97-08-01 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
1999 may 27 32 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 may 27 33 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
1999 may 27 34 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. bare die disclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there is no post waffle pack testing performed on individual die. although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, philips semiconductors has no control of third party procedures in the handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1999 may 27 35 philips semiconductors product speci?cation sdh/sonet data and clock recovery unit stm1/4/16 oc3/12/48 ge OQ2541hp; OQ2541u notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 65 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 02 67 52 2531, fax. +39 02 67 52 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 465012/150/03/pp36 date of release: 1999 may 27 document order number: 9397 750 05019

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